The continued shrinking of process geometries in complementary metal oxide semiconductor (CMOS) technologies has led to unprecedented growth in the processing power of digital computing systems. While these systems are predominantly composed of digital circuits, they also contain some high performance analog circuits. For example, circuits for inter-chip communication employ high-speed amplifiers and equalizers in their datapath. Operation at reduced supply voltages is one of the most difficult challenges in designing these analog circuits in modern deep sub-micron CMOS technologies. In particular, reduced supply voltages make it difficult to choose output common-mode voltages for these amplifiers that are suitable for meeting their gain and linearity requirements.